Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.
Power Reduction using Vivado
FPGA

Power Reduction using Vivado

An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
FPGA

Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
Investigating Xilinx AXI IP and Registered Outputs
FPGA

Investigating Xilinx AXI IP and Registered Outputs

Investigating Xilinx AXI IP Cores, registered outputs and the AXI specification using equivalent components for the AXI stream split and join functions.
Determining A Device's Maximum Clock Speed
FPGA

Determining A Device's Maximum Clock Speed

A proposed method for determining an FPGA device's maximum clock speed.
Doulos Clock Domain Crossing Material
VHDL

Doulos Clock Domain Crossing Material

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
AXI-Stream Split & Join Components
VHDL

AXI-Stream Split & Join Components

Trivial but useful to have as reference code
Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM
FPGA

Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM

A neat trick to take advantage of a pipelining opportunity with XPM RAM.
Dynamic Timing Check For A Standard Clock Domain Crossing Solution
VHDL

Dynamic Timing Check For A Standard Clock Domain Crossing Solution

This is a standard clock domain crossing solution however what is often overlooked in the implementation is the constraint that the inputs must remain stable long enough to be safely sampled by the destination clock domain. This requires a dynamic check…
Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.