Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.
Dynamic Function eXchange with ICAP Driven by Software
FPGA

Dynamic Function eXchange with ICAP Driven by Software

With the previous success of reconfiguring removable partitions via the ICAP interface, what does the AXI-lite interface allow software to do?
Dynamic Function eXchange with ICAP
FPGA

Dynamic Function eXchange with ICAP

With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
Explaining Minimum Output Delays
FPGA

Explaining Minimum Output Delays

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
Dynamic Function eXchange
FPGA

Dynamic Function eXchange

FPGA partial reconfiguration using a very basic demonstration design.
01 Signal Sampling
FPGA

01 Signal Sampling

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
Low Speed Serial I/O
FPGA

Low Speed Serial I/O

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…
Assertion-based Verification in Intel's Free QuestaSim
VHDL

Assertion-based Verification in Intel's Free QuestaSim

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
Large Multiplexer Pipelined Efficiently by Recursion
VHDL

Large Multiplexer Pipelined Efficiently by Recursion

Creating an excessively large multiplexer component that is arbitraily pipelined.
Large Barrel Shift Pipelined by Iteration or Recursion
VHDL

Large Barrel Shift Pipelined by Iteration or Recursion

Creating an excessively large barrel shift component that is arbitraily pipelined.