Creating an excessively large multiplexer component that is arbitraily pipelined.
VHDL
Large Barrel Shift Pipelined by Iteration or Recursion
Creating an excessively large barrel shift component that is arbitraily pipelined.
VHDL
Multiple Bit Pseudorandom Binary Sequence
The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.
FPGA
Power Reduction using Vivado
An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
FPGA
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
FPGA
Investigating Xilinx AXI IP and Registered Outputs
Investigating Xilinx AXI IP Cores, registered outputs and the AXI specification using equivalent components for the AXI stream split and join functions.
FPGA
Determining A Device's Maximum Clock Speed
A proposed method for determining an FPGA device's maximum clock speed.
VHDL
Doulos Clock Domain Crossing Material
Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
