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Thank you, I think I have found the replacement at https://support.xilinx.com/s/question/0D52E00006hpKmUSAU/timing-summary-understanding?language=en_US and now updated the link above.

It is also worth noting that you can update a VHDL signal from TCL using the force command:
force -deposit <signal_name> <value></value></signal_name>

This means that bidirectional communication between TCL and VHDL is possible.