In response to: Taking Xilinx's Advice on Reducing Routing Congestion
Comment from: philip Member

Thank you!
Thank you!
Thank you for your kind words.
Philip
I’ve just discovered this blog post and I’d like to thank you for it.
This post, just like the whole blog is just great!
Thank you, I think I have found the replacement at https://support.xilinx.com/s/question/0D52E00006hpKmUSAU/timing-summary-understanding?language=en_US and now updated the link above.
It is also worth noting that you can update a VHDL signal from TCL using the force
command:
force -deposit <signal_name> <value></value></signal_name>
This means that bidirectional communication between TCL and VHDL is possible.
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