Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
FPGA
Investigating Xilinx AXI IP and Registered Outputs
Investigating Xilinx AXI IP Cores, registered outputs and the AXI specification using equivalent components for the AXI stream split and join functions.
FPGA
Determining A Device's Maximum Clock Speed
A proposed method for determining an FPGA device's maximum clock speed.
VHDL
Doulos Clock Domain Crossing Material
Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
VHDL
AXI-Stream Split & Join Components
Trivial but useful to have as reference code
FPGA
Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM
A neat trick to take advantage of a pipelining opportunity with XPM RAM.
VHDL
Dynamic Timing Check For A Standard Clock Domain Crossing Solution
This is a standard clock domain crossing solution however what is often overlooked in the implementation is the constraint that the inputs must remain stable long enough to be safely sampled by the destination clock domain. This requires a dynamic check…
FPGA
Practical Control Set Reduction
Checking that control set remapping delivers on the Xilinx promises.
FPGA
Exploring Xilinx XPM Memory
The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
