Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.
Cygwin Mirror and Installation
Bash

Cygwin Mirror and Installation

Ensuring that your whole team has the same repeatable installation of Cygwin. How to mirror Cygwin on to local infrastructure such that you can script the installation to be the same for everyone.
Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
VHDL

Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'

Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
Using Python Decorators
Python

Using Python Decorators

A python decorator allows you to remove repeated code by passing function into another function which extends it.
Deriving AXI Crossbar Address Maps
FPGA

Deriving AXI Crossbar Address Maps

Some tips and tricks for correctly decoding an AXI crossbar address map.
Resilient Xilinx Vivado Licence Acquisition
FPGA

Resilient Xilinx Vivado Licence Acquisition

Our design team has recently observed that Vivado has been struggling to get a licence later into long running compilations. These are some of the ideas I have developed to try and monitor the problem and make our compilations resilient to licence…
Automating Code Review Design Checks in Vivado
FPGA

Automating Code Review Design Checks in Vivado

Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
Writing a simple Garmin app for my watch
Garmin-ConnectIQ

Writing a simple Garmin app for my watch

I am going to be writing an app for my watch to control my family's amplifier.
Visualising Clock Domain Crossings in Vivado
FPGA

Visualising Clock Domain Crossings in Vivado

When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
Specifying Boundary Timing Constraints in Vivado
FPGA

Specifying Boundary Timing Constraints in Vivado

How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.