FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
VHDL
Compiling VHDL For The Missing Fixed And Floating Point Libraries
VHDL-2008 has added types sfixed, ufixed and float for fixed and floating point arithmetic, but you may struggle to use them with older tools. Here's how to fix that.
VHDL
FIR Filter Implementation Comparisons
Having created the pipelined adder tree component, time to compare it with other implementations to see what value it adds.
VHDL
Adder Trees Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
FPGA
Notes on Fixing Hold Time Violations
Gathering advice on how to fix hold time violations with an emphasis on FPGA design.
Bash
Cygwin Mirror and Installation
Ensuring that your whole team has the same repeatable installation of Cygwin. How to mirror Cygwin on to local infrastructure such that you can script the installation to be the same for everyone.
VHDL
Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
Python
Using Python Decorators
A python decorator allows you to remove repeated code by passing function into another function which extends it.
FPGA
Deriving AXI Crossbar Address Maps
Some tips and tricks for correctly decoding an AXI crossbar address map.
