Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
FPGA
Notes on Fixing Hold Time Violations
Gathering advice on how to fix hold time violations with an emphasis on FPGA design.
Bash
Cygwin Mirror and Installation
Ensuring that your whole team has the same repeatable installation of Cygwin. How to mirror Cygwin on to local infrastructure such that you can script the installation to be the same for everyone.
VHDL
Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
Python
Using Python Decorators
A python decorator allows you to remove repeated code by passing function into another function which extends it.
FPGA
Deriving AXI Crossbar Address Maps
Some tips and tricks for correctly decoding an AXI crossbar address map.
FPGA
Resilient Xilinx Vivado Licence Acquisition
Our design team has recently observed that Vivado has been struggling to get a licence later into long running compilations. These are some of the ideas I have developed to try and monitor the problem and make our compilations resilient to licence…
FPGA
Automating Code Review Design Checks in Vivado
Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
Garmin-ConnectIQ
Writing a simple Garmin app for my watch
I am going to be writing an app for my watch to control my family's amplifier.
