Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
Python
Using Python Decorators
A python decorator allows you to remove repeated code by passing function into another function which extends it.
FPGA
Deriving AXI Crossbar Address Maps
Some tips and tricks for correctly decoding an AXI crossbar address map.
FPGA
Resilient Xilinx Vivado Licence Acquisition
Our design team has recently observed that Vivado has been struggling to get a licence later into long running compilations. These are some of the ideas I have developed to try and monitor the problem and make our compilations resilient to licence…
FPGA
Automating Code Review Design Checks in Vivado
Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
Garmin-ConnectIQ
Writing a simple Garmin app for my watch
I am going to be writing an app for my watch to control my family's amplifier.
FPGA
Visualising Clock Domain Crossings in Vivado
When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
FPGA
Specifying Boundary Timing Constraints in Vivado
How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.
Web Authoring
Reverse Engineering the Denon Amplifier Web API
We've just purchased a Denon AVR-X3700H AV amplifier. We're now reverse engineering how the web-based application works, and potentially the Android App too, so that we can detail what HTTP GET requests we can make when building our own automation…
