We've just purchased a Denon AVR-X3700H AV amplifier. We're now reverse engineering how the web-based application works, and potentially the Android App too, so that we can detail what HTTP GET requests we can make when building our own automation…
FPGA
Interpreting The AXI Protocol Specification for Testing
Interpreting the ARM AMBA AXI protocol specification so that hardware components can be successfully created and tested.
Web Authoring
MathJax Plugin For b2Evolution
Creating equations in b2Evolution.
Web Authoring
WaveDrom Plugin For b2Evolution
Creating logic timing diagrams for b2Evolution.
Arduino
Arduino - From INO to Python
A guided tour around the Arduino (UNO) and it capabilities.
VHDL
Cascade Block RAMs for Larger Memories
Making the least of Xilinx BlockRAM "cascade logic" for performance.
VHDL
SRL Inferencing with Xilinx FPGAs
The inference of Xilinx SRLs is often believed to be dependent on the inclusion of a reset condition. Since the SRL does not have a reset input, it is logical that to infer use of SRLs, the HDL code must also exclude a reset pin. Or is it?
DSP
Digital Audio Projects
Having purchased Arm's Online DSP Course and completed it, here are a few projects I tried based on note I found on-line written by Prof. Dave Marshall at Cardiff School of Computer Science.
