A guided tour around the Arduino (UNO) and it capabilities.
VHDL
Cascade Block RAMs for Larger Memories
Making the least of Xilinx BlockRAM "cascade logic" for performance.
VHDL
SRL Inferencing with Xilinx FPGAs
The inference of Xilinx SRLs is often believed to be dependent on the inclusion of a reset condition. Since the SRL does not have a reset input, it is logical that to infer use of SRLs, the HDL code must also exclude a reset pin. Or is it?
DSP
Digital Audio Projects
Having purchased Arm's Online DSP Course and completed it, here are a few projects I tried based on note I found on-line written by Prof. Dave Marshall at Cardiff School of Computer Science.
DSP
Some notes on using the Keil Debugger
Had a few issues, found a couple of solutions.
DSP
An Inexpensive Digital Signal Processing Course with Practicals
Exploring using the Arm's Online DSP Course for home-based study with minimal equipment to purchase.
VHDL
Large Comparators Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a mathematics problem, and once the VHDL construction has been completed, the EDA tools have a final twist.
VHDL
Bus-width Polynomial Division Logic
Calculating the remainder after polynomial division modulo 2 multiple bits per clock cycle. This enables the calculation to keep pace with the presentation of a wide data bus. This article shows how VHDL and synthesis can automatically calculate the…
VHDL
Swapping Synchronous and LFSR Counters
Easily replace synchronous counters with equivalent LFSR-based fast counters.
