My first attempt at using Vitis HLS to synthesise C code to logic.

The question came up at work, is inferred RAM compatible across different FPGA vendors?

Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.

With the previous success of reconfiguring removable partitions via the ICAP interface, what does the AXI-lite interface allow software to do?

With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.

FPGA partial reconfiguration using a very basic demonstration design.

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does not offer a reduce power solution from a lower clock speed.

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.

Creating an excessively large multiplexer component that is arbitraily pipelined.

Creating an excessively large barrel shift component that is arbitraily pipelined.

The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.

An attempt to reduce power consumption of a simple design using Vivado's power_opt_design.

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.