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In response to: Specifying Boundary Timing Constraints in Vivado

2026-05-02T17:08:22Z

Thank you for the compliment.

> How did you create these pictures? is there a tool for that?

Just Microsoft PowerPoint, other drawing packages are available…

In response to: Specifying Boundary Timing Constraints in Vivado

2026-05-02T14:12:25Z

Hey!
Thank you for nice article.
How did you create these pictures? is there a tool for that?

In response to: Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

2025-10-16T15:02:04Z

Vivado IP is the next level of abstraction up. You would need to generate the FIR filter and then figure out which files you needed to include in your broader compile script. For example:

PLL:

pll\pll_sim_netlist.vhdl

AXI IP:

axis_broadcaster\gen\axis_broadcaster_sim_netlist.vhdl
axis_combiner\gen\axis_combiner_sim_netlist.vhdl
axis_register_slice\gen\axis_register_slice_sim_netlist.vhdl

DFX Controller: You will need something more elaborate like https://github.com/philipabbey/fpga/blob/main/VHDL/DFX_PS/modelsim_compile.cmd

There’s no simple answer here, you have to do the hard work to figure it out. Good Luck!

In response to: Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

2025-10-16T14:49:25Z

Hey!

how can I compile xilinx IP like for example FIR compiler with this?

In response to: Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

2025-09-30T15:30:55Z

Thank you for taking the time to post your appreciation. I think you have spotted a mistake and I need to re-test with your correction.

The AMD/Xilinx question states “This question is closed", so I can’t add anything new to it. Perhaps one day I will get a reddit account and post there, but feel free to make the link yourself.

Best wishes,

Philip

In response to: Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

2025-09-30T08:37:11Z

Hi,

I want to thank you for this post, I don’t have deep knowledge of TCL and without this post I don’t think I would have been able to use the Vivado libraries in QuestaSim.

I think this post is much more useful than the two posts you quote from the AMD forum and Reddit so I encourage you to write an entry in that Reddit post with the link to this website, as it appears much higher than this website in Google searches.

Just a comment: when you compile the XPM library on lines 142-145 I think the correct path to the FIFOs package is
"%xpm%\xpm_fifo\hdl\xpm_fifo.sv" ^
instead of
"%xpm%\xpm_fifo\simulation\xpm_fifo_tb.sv" ^
Or at least that’s how it worked for me.

Regards,

Pablo

In response to: Low Speed Serial I/O Variable Delay Monitoring

2025-08-17T10:51:13Z

Xilinx would appear to have already written an IP core for their FPGAs according to this document: LDPC Encoder Decoder v1.0 Product Brief (PB052)

In response to: Low Speed Serial I/O Variable Delay Monitoring

2025-08-16T16:29:03Z

No! I’m afraid I had to look Low-density parity-check code up on Wikipedia. I will have to consider that, thanks for the pointer. I did find the 01 signal sampling was superior to these methods. BTW I am currently double checking my work here as it happens.