Technology Blogs

First Attempt at High Level Synthesis

Philip — Fri, 24 Apr 2026 14:35:00 +0000

My first attempt at using Vitis HLS to synthesise C code to logic.

Original post blogged on b2evolution.

Cross-vendor Compatibility of VHDL Inferred RAM

Philip — Thu, 16 Oct 2025 17:41:00 +0000

The question came up at work, is inferred RAM compatible across different FPGA vendors?

Original post blogged on b2evolution.

Low Speed Serial I/O Variable Delay Monitoring

Philip — Mon, 04 Aug 2025 21:14:00 +0000

Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.

Original post blogged on b2evolution.

Dynamic Function eXchange with ICAP Driven by Software

Philip — Mon, 05 May 2025 18:09:00 +0000

With the previous success of reconfiguring removable partitions via the ICAP interface, what does the AXI-lite interface allow software to do?

Original post blogged on b2evolution.

Dynamic Function eXchange with ICAP

Philip — Thu, 01 May 2025 20:01:00 +0000

With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?

Original post blogged on b2evolution.

Explaining Minimum Output Delays

Philip — Wed, 12 Mar 2025 18:12:00 +0000

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.

Original post blogged on b2evolution.

Dynamic Function eXchange

Philip — Fri, 14 Feb 2025 19:14:00 +0000

FPGA partial reconfiguration using a very basic demonstration design.

Original post blogged on b2evolution.

01 Signal Sampling

Philip — Fri, 03 Jan 2025 14:55:00 +0000

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.

Original post blogged on b2evolution.

Low Speed Serial I/O

Philip — Sat, 28 Dec 2024 16:58:00 +0000

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does not offer a reduce power solution from a lower clock speed.

Original post blogged on b2evolution.

Assertion-based Verification in Intel's Free QuestaSim

Philip — Mon, 16 Dec 2024 21:16:00 +0000

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.

Original post blogged on b2evolution.

Large Multiplexer Pipelined Efficiently by Recursion

Philip — Fri, 29 Nov 2024 18:15:00 +0000

Creating an excessively large multiplexer component that is arbitraily pipelined.

Original post blogged on b2evolution.

Large Barrel Shift Pipelined by Iteration or Recursion

Philip — Fri, 22 Nov 2024 17:21:00 +0000

Creating an excessively large barrel shift component that is arbitraily pipelined.

Original post blogged on b2evolution.

Multiple Bit Pseudorandom Binary Sequence

Philip — Sun, 17 Nov 2024 19:21:00 +0000

The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.

Original post blogged on b2evolution.

Power Reduction using Vivado

Philip — Sun, 13 Oct 2024 18:16:00 +0000

An attempt to reduce power consumption of a simple design using Vivado's power_opt_design.

Original post blogged on b2evolution.

Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

Philip — Sun, 06 Oct 2024 12:53:00 +0000

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.

Original post blogged on b2evolution.