We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "axi"

Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM
FPGA

Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM

A neat trick to take advantage of a pipelining opportunity with XPM RAM.
AXI Stream Protocol Editing
VHDL

AXI Stream Protocol Editing

Example use of the 'AXI Edit' component to convert a protocol.
AXI Stream General Edit
VHDL

AXI Stream General Edit

A general way of editing an AXI stream using actions: pass, swap, drop, insert and pause.
AXI Data Stream Width Conversion
VHDL

AXI Data Stream Width Conversion

Example code to convert 16-bit data to 8-bits in an AXI Data Stream.
Working With AXI Streaming Data
VHDL

Working With AXI Streaming Data

Beyond using Xilinx IP cores to work with AXI streaming data, one will always need to eventually write custom VHDL code. I've personally found working with AXI awkward and so I've put together some techniques.
Deriving AXI Crossbar Address Maps
FPGA

Deriving AXI Crossbar Address Maps

Some tips and tricks for correctly decoding an AXI crossbar address map.
Interpreting The AXI Protocol Specification for Testing
FPGA

Interpreting The AXI Protocol Specification for Testing

Interpreting the ARM AMBA AXI protocol specification so that hardware components can be successfully created and tested.