Assertion-based Verification in Intel's Free QuestaSim
Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
FPGA
Investigating Xilinx AXI IP and Registered Outputs
Investigating Xilinx AXI IP Cores, registered outputs and the AXI specification using equivalent components for the AXI stream split and join functions.
VHDL
AXI-Stream Split & Join Components
Trivial but useful to have as reference code
FPGA
Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM
A neat trick to take advantage of a pipelining opportunity with XPM RAM.
VHDL
AXI Stream Protocol Editing
Example use of the 'AXI Edit' component to convert a protocol.
VHDL
AXI Stream General Edit
A general way of editing an AXI stream using actions: pass, swap, drop, insert and pause.
VHDL
AXI Data Stream Width Conversion
Example code to convert 16-bit data to 8-bits in an AXI Data Stream.
VHDL
Working With AXI Streaming Data
Beyond using Xilinx IP cores to work with AXI streaming data, one will always need to eventually write custom VHDL code. I've personally found working with AXI awkward and so I've put together some techniques.
FPGA
Deriving AXI Crossbar Address Maps
Some tips and tricks for correctly decoding an AXI crossbar address map.
