We play with technology. Sometimes we discover things we think are worth sharing.
Tag: "clock domain crossing"
FPGA
01 Signal Sampling
Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
VHDL
Doulos Clock Domain Crossing Material
Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
VHDL
Dynamic Timing Check For A Standard Clock Domain Crossing Solution
This is a standard clock domain crossing solution however what is often overlooked in the implementation is the constraint that the inputs must remain stable long enough to be safely sampled by the destination clock domain. This requires a dynamic check…
FPGA
Managing Mean Time Between Failure in Xilinx Devices
The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…
FPGA
Verification of Clock Domain Crossing Topologies
There are too many ways in which it is possible to mess up clock domain crossings in digital electronics. This post explores Xilinx's report_cdc TCL command and how well it recognises some of the risks you may have missed.
FPGA
Verification of Clock Domain Crossing Timing Constraints and Exceptions
Applying timing exceptions for synchronising registers when crossing clock domains, and verifying the exceptions have been correctly applied and others have not been missed.
FPGA
Automating Code Review Design Checks in Vivado
Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
FPGA
Visualising Clock Domain Crossings in Vivado
When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
