Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "constraints"

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Explaining Minimum Output Delays
FPGA

Explaining Minimum Output Delays

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
Dynamic Function eXchange
FPGA

Dynamic Function eXchange

FPGA partial reconfiguration using a very basic demonstration design.
01 Signal Sampling
FPGA

01 Signal Sampling

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
Low Speed Serial I/O
FPGA

Low Speed Serial I/O

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…
Determining A Device's Maximum Clock Speed
FPGA

Determining A Device's Maximum Clock Speed

A proposed method for determining an FPGA device's maximum clock speed.
Doulos Clock Domain Crossing Material
VHDL

Doulos Clock Domain Crossing Material

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
Dynamic Timing Check For A Standard Clock Domain Crossing Solution
VHDL

Dynamic Timing Check For A Standard Clock Domain Crossing Solution

This is a standard clock domain crossing solution however what is often overlooked in the implementation is the constraint that the inputs must remain stable long enough to be safely sampled by the destination clock domain. This requires a dynamic check…
Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.
Taking Xilinx's Advice on Reducing Routing Congestion
FPGA

Taking Xilinx's Advice on Reducing Routing Congestion

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
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