We play with technology. Sometimes we discover things we think are worth sharing.
Tag: "control sets"
FPGA
Power Reduction using Vivado
An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
FPGA
Practical Control Set Reduction
Checking that control set remapping delivers on the Xilinx promises.
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
