Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Category: "FPGA"

Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.
Exploring Xilinx XPM Memory
FPGA

Exploring Xilinx XPM Memory

The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
AXI Stream Protocol Editing
VHDL

AXI Stream Protocol Editing

Example use of the 'AXI Edit' component to convert a protocol.
AXI Stream General Edit
VHDL

AXI Stream General Edit

A general way of editing an AXI stream using actions: pass, swap, drop, insert and pause.
AXI Data Stream Width Conversion
VHDL

AXI Data Stream Width Conversion

Example code to convert 16-bit data to 8-bits in an AXI Data Stream.
Taking Xilinx's Advice on Reducing Routing Congestion
FPGA

Taking Xilinx's Advice on Reducing Routing Congestion

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
Extracting Setup and Hold Times from Devices for Out of Context Synthesis
TCL

Extracting Setup and Hold Times from Devices for Out of Context Synthesis

The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…
Determining Port Clock Domains for Automating Input and Output Constraints
TCL

Determining Port Clock Domains for Automating Input and Output Constraints

When initially looking at setting up out of context synthesis, one of the early goals was to automate the discovery of which clock domain each input and output port is in. Sadly, it got complicated and then bogged down until it became a hindrance to…
Managing Mean Time Between Failure in Xilinx Devices
FPGA

Managing Mean Time Between Failure in Xilinx Devices

The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…