We play with technology. Sometimes we discover things we think are worth sharing.
Tag: "inferencing"
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
FPGA
Automating Code Review Design Checks in Vivado
Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
VHDL
Cascade Block RAMs for Larger Memories
Making the least of Xilinx BlockRAM "cascade logic" for performance.
VHDL
SRL Inferencing with Xilinx FPGAs
The inference of Xilinx SRLs is often believed to be dependent on the inclusion of a reset condition. Since the SRL does not have a reset input, it is logical that to infer use of SRLs, the HDL code must also exclude a reset pin. Or is it?
