We play with technology. Sometimes we discover things we think are worth sharing.
Tag: "meta-stability"
FPGA
01 Signal Sampling
Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
FPGA
Managing Mean Time Between Failure in Xilinx Devices
The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…
FPGA
Verification of Clock Domain Crossing Timing Constraints and Exceptions
Applying timing exceptions for synchronising registers when crossing clock domains, and verifying the exceptions have been correctly applied and others have not been missed.
FPGA
Notes on Fixing Hold Time Violations
Gathering advice on how to fix hold time violations with an emphasis on FPGA design.
FPGA
Visualising Clock Domain Crossings in Vivado
When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
FPGA
Specifying Boundary Timing Constraints in Vivado
How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.
