A general way of editing an AXI stream using actions: pass, swap, drop, insert and pause.
TCL
TCL/TK Graphical Display Driven By A VHDL Test Bench
An example TCK/TK graphical display driven by VHDL such that as signals change, the display reflects the new values.
FPGA
Getting Started with FPGA and VHDL
I've been asked a few times how one gets started with FPGA design? Here are a few notes on the tools you can download for free and the existing websites that already cater for teaching VHDL.
VHDL
Working With AXI Streaming Data
Beyond using Xilinx IP cores to work with AXI streaming data, one will always need to eventually write custom VHDL code. I've personally found working with AXI awkward and so I've put together some techniques.
VHDL
Radix-n Fast Fourier Transforms (Part 2)
FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
VHDL
Radix-n Fast Fourier Transforms (Part 1)
FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
VHDL
Compiling VHDL For The Missing Fixed And Floating Point Libraries
VHDL-2008 has added types sfixed, ufixed and float for fixed and floating point arithmetic, but you may struggle to use them with older tools. Here's how to fix that.
VHDL
Adder Trees Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
VHDL
Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
