Large Multiplexer Pipelined Efficiently by Recursion
Creating an excessively large multiplexer component that is arbitraily pipelined.
FPGA
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
FPGA
Getting Started with FPGA and VHDL
I've been asked a few times how one gets started with FPGA design? Here are a few notes on the tools you can download for free and the existing websites that already cater for teaching VHDL.
VHDL
Radix-n Fast Fourier Transforms (Part 3)
FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
VHDL
Compiling VHDL For The Missing Fixed And Floating Point Libraries
VHDL-2008 has added types sfixed, ufixed and float for fixed and floating point arithmetic, but you may struggle to use them with older tools. Here's how to fix that.
VHDL
FIR Filter Implementation Comparisons
Having created the pipelined adder tree component, time to compare it with other implementations to see what value it adds.
VHDL
Adder Trees Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
VHDL
Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
