We play with technology. Sometimes we discover things we think are worth sharing.
Tag: "ram"
FPGA
Exploring Xilinx XPM Memory
The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
FPGA
Verification of Clock Domain Crossing Topologies
There are too many ways in which it is possible to mess up clock domain crossings in digital electronics. This post explores Xilinx's report_cdc TCL command and how well it recognises some of the risks you may have missed.
VHDL
Cascade Block RAMs for Larger Memories
Making the least of Xilinx BlockRAM "cascade logic" for performance.
