Technology Blogs

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Tag: "setup"

Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.
Extracting Setup and Hold Times from Devices for Out of Context Synthesis
TCL

Extracting Setup and Hold Times from Devices for Out of Context Synthesis

The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…
Managing Mean Time Between Failure in Xilinx Devices
FPGA

Managing Mean Time Between Failure in Xilinx Devices

The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…
Specifying Boundary Timing Constraints in Vivado
FPGA

Specifying Boundary Timing Constraints in Vivado

How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.