Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "synthesis"

Large Multiplexer Pipelined Efficiently by Recursion
VHDL

Large Multiplexer Pipelined Efficiently by Recursion

Creating an excessively large multiplexer component that is arbitraily pipelined.
Large Barrel Shift Pipelined by Iteration or Recursion
VHDL

Large Barrel Shift Pipelined by Iteration or Recursion

Creating an excessively large barrel shift component that is arbitraily pipelined.
Power Reduction using Vivado
FPGA

Power Reduction using Vivado

An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
Doulos Clock Domain Crossing Material
VHDL

Doulos Clock Domain Crossing Material

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.
Exploring Xilinx XPM Memory
FPGA

Exploring Xilinx XPM Memory

The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
Taking Xilinx's Advice on Reducing Routing Congestion
FPGA

Taking Xilinx's Advice on Reducing Routing Congestion

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
Extracting Setup and Hold Times from Devices for Out of Context Synthesis
TCL

Extracting Setup and Hold Times from Devices for Out of Context Synthesis

The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…
Determining Port Clock Domains for Automating Input and Output Constraints
TCL

Determining Port Clock Domains for Automating Input and Output Constraints

When initially looking at setting up out of context synthesis, one of the early goals was to automate the discovery of which clock domain each input and output port is in. Sadly, it got complicated and then bogged down until it became a hindrance to…