With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
FPGA
Dynamic Function eXchange
FPGA partial reconfiguration using a very basic demonstration design.
VHDL
Large Multiplexer Pipelined Efficiently by Recursion
Creating an excessively large multiplexer component that is arbitraily pipelined.
VHDL
Large Barrel Shift Pipelined by Iteration or Recursion
Creating an excessively large barrel shift component that is arbitraily pipelined.
FPGA
Power Reduction using Vivado
An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
VHDL
Doulos Clock Domain Crossing Material
Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
FPGA
Practical Control Set Reduction
Checking that control set remapping delivers on the Xilinx promises.
FPGA
Exploring Xilinx XPM Memory
The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
