Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Category: "TCL"

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Extracting Setup and Hold Times from Devices for Out of Context Synthesis
TCL

Extracting Setup and Hold Times from Devices for Out of Context Synthesis

The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…
Determining Port Clock Domains for Automating Input and Output Constraints
TCL

Determining Port Clock Domains for Automating Input and Output Constraints

When initially looking at setting up out of context synthesis, one of the early goals was to automate the discovery of which clock domain each input and output port is in. Sadly, it got complicated and then bogged down until it became a hindrance to…
Managing Mean Time Between Failure in Xilinx Devices
FPGA

Managing Mean Time Between Failure in Xilinx Devices

The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…
TCL/TK Graphical Display Driven By A VHDL Test Bench
TCL

TCL/TK Graphical Display Driven By A VHDL Test Bench

An example TCK/TK graphical display driven by VHDL such that as signals change, the display reflects the new values.
Verification of Clock Domain Crossing Topologies
FPGA

Verification of Clock Domain Crossing Topologies

There are too many ways in which it is possible to mess up clock domain crossings in digital electronics. This post explores Xilinx's report_cdc TCL command and how well it recognises some of the risks you may have missed.
Verification of Clock Domain Crossing Timing Constraints and Exceptions
FPGA

Verification of Clock Domain Crossing Timing Constraints and Exceptions

Applying timing exceptions for synchronising registers when crossing clock domains, and verifying the exceptions have been correctly applied and others have not been missed.
Resilient Xilinx Vivado Licence Acquisition
FPGA

Resilient Xilinx Vivado Licence Acquisition

Our design team has recently observed that Vivado has been struggling to get a licence later into long running compilations. These are some of the ideas I have developed to try and monitor the problem and make our compilations resilient to licence…
Automating Code Review Design Checks in Vivado
FPGA

Automating Code Review Design Checks in Vivado

Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
Visualising Clock Domain Crossings in Vivado
FPGA

Visualising Clock Domain Crossings in Vivado

When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
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