Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "tcl"

Low Speed Serial I/O Variable Delay Monitoring
FPGA

Low Speed Serial I/O Variable Delay Monitoring

Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.
Dynamic Function eXchange with ICAP
FPGA

Dynamic Function eXchange with ICAP

With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
Dynamic Function eXchange
FPGA

Dynamic Function eXchange

FPGA partial reconfiguration using a very basic demonstration design.
01 Signal Sampling
FPGA

01 Signal Sampling

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
Low Speed Serial I/O
FPGA

Low Speed Serial I/O

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…
Power Reduction using Vivado
FPGA

Power Reduction using Vivado

An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
FPGA

Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
Determining A Device's Maximum Clock Speed
FPGA

Determining A Device's Maximum Clock Speed

A proposed method for determining an FPGA device's maximum clock speed.
Doulos Clock Domain Crossing Material
VHDL

Doulos Clock Domain Crossing Material

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.