Technology Blogs

FPGA partial reconfiguration using a very basic demonstration design.

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…

An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.

A proposed method for determining an FPGA device's maximum clock speed.

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.

The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…