Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "timing"

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Dynamic Timing Check For A Standard Clock Domain Crossing Solution
VHDL

Dynamic Timing Check For A Standard Clock Domain Crossing Solution

This is a standard clock domain crossing solution however what is often overlooked in the implementation is the constraint that the inputs must remain stable long enough to be safely sampled by the destination clock domain. This requires a dynamic check…
Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.
Taking Xilinx's Advice on Reducing Routing Congestion
FPGA

Taking Xilinx's Advice on Reducing Routing Congestion

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
Extracting Setup and Hold Times from Devices for Out of Context Synthesis
TCL

Extracting Setup and Hold Times from Devices for Out of Context Synthesis

The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…
Determining Port Clock Domains for Automating Input and Output Constraints
TCL

Determining Port Clock Domains for Automating Input and Output Constraints

When initially looking at setting up out of context synthesis, one of the early goals was to automate the discovery of which clock domain each input and output port is in. Sadly, it got complicated and then bogged down until it became a hindrance to…
Managing Mean Time Between Failure in Xilinx Devices
FPGA

Managing Mean Time Between Failure in Xilinx Devices

The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…
Getting Started with FPGA and VHDL
FPGA

Getting Started with FPGA and VHDL

I've been asked a few times how one gets started with FPGA design? Here are a few notes on the tools you can download for free and the existing websites that already cater for teaching VHDL.
Verification of Clock Domain Crossing Topologies
FPGA

Verification of Clock Domain Crossing Topologies

There are too many ways in which it is possible to mess up clock domain crossings in digital electronics. This post explores Xilinx's report_cdc TCL command and how well it recognises some of the risks you may have missed.
Working With AXI Streaming Data
VHDL

Working With AXI Streaming Data

Beyond using Xilinx IP cores to work with AXI streaming data, one will always need to eventually write custom VHDL code. I've personally found working with AXI awkward and so I've put together some techniques.
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