We play with technology. Sometimes we discover things we think are worth sharing.

Category: "VHDL"

Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM
FPGA

Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM

A neat trick to take advantage of a pipelining opportunity with XPM RAM.
Dynamic Timing Check For A Standard Clock Domain Crossing Solution
VHDL

Dynamic Timing Check For A Standard Clock Domain Crossing Solution

This is a standard clock domain crossing solution however what is often overlooked in the implementation is the constraint that the inputs must remain stable long enough to be safely sampled by the destination clock domain. This requires a dynamic check…
Exploring Xilinx XPM Memory
FPGA

Exploring Xilinx XPM Memory

The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
A Crib For Formatting Strings in VHDL
VHDL

A Crib For Formatting Strings in VHDL

VHDL solutions I keep searching the Internet for, so I've created a crib.
AXI Stream Protocol Editing
VHDL

AXI Stream Protocol Editing

Example use of the 'AXI Edit' component to convert a protocol.
AXI Stream General Edit
VHDL

AXI Stream General Edit

A general way of editing an AXI stream using actions: pass, swap, drop, insert and pause.
AXI Data Stream Width Conversion
VHDL

AXI Data Stream Width Conversion

Example code to convert 16-bit data to 8-bits in an AXI Data Stream.
Taking Xilinx's Advice on Reducing Routing Congestion
FPGA

Taking Xilinx's Advice on Reducing Routing Congestion

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
Managing Mean Time Between Failure in Xilinx Devices
FPGA

Managing Mean Time Between Failure in Xilinx Devices

The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…