Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Category: "VHDL"

Dynamic Function eXchange
FPGA

Dynamic Function eXchange

FPGA partial reconfiguration using a very basic demonstration design.
Assertion-based Verification in Intel's Free QuestaSim
VHDL

Assertion-based Verification in Intel's Free QuestaSim

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
Large Multiplexer Pipelined Efficiently by Recursion
VHDL

Large Multiplexer Pipelined Efficiently by Recursion

Creating an excessively large multiplexer component that is arbitraily pipelined.
Large Barrel Shift Pipelined by Iteration or Recursion
VHDL

Large Barrel Shift Pipelined by Iteration or Recursion

Creating an excessively large barrel shift component that is arbitraily pipelined.
Multiple Bit Pseudorandom Binary Sequence
VHDL

Multiple Bit Pseudorandom Binary Sequence

The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.
Determining A Device's Maximum Clock Speed
FPGA

Determining A Device's Maximum Clock Speed

A proposed method for determining an FPGA device's maximum clock speed.
Doulos Clock Domain Crossing Material
VHDL

Doulos Clock Domain Crossing Material

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
AXI-Stream Split & Join Components
VHDL

AXI-Stream Split & Join Components

Trivial but useful to have as reference code
Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM
FPGA

Implementing an AXI-Streaming delay pipeline when reading data from XPM RAM

A neat trick to take advantage of a pipelining opportunity with XPM RAM.