We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "intel"

Explaining Minimum Output Delays
FPGA

Explaining Minimum Output Delays

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
Assertion-based Verification in Intel's Free QuestaSim
VHDL

Assertion-based Verification in Intel's Free QuestaSim

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
FPGA

Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
Taking Xilinx's Advice on Reducing Routing Congestion
FPGA

Taking Xilinx's Advice on Reducing Routing Congestion

I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
Getting Started with FPGA and VHDL
FPGA

Getting Started with FPGA and VHDL

I've been asked a few times how one gets started with FPGA design? Here are a few notes on the tools you can download for free and the existing websites that already cater for teaching VHDL.
Radix-n Fast Fourier Transforms (Part 3)
VHDL

Radix-n Fast Fourier Transforms (Part 3)

FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
Compiling VHDL For The Missing Fixed And Floating Point Libraries
VHDL

Compiling VHDL For The Missing Fixed And Floating Point Libraries

VHDL-2008 has added types sfixed, ufixed and float for fixed and floating point arithmetic, but you may struggle to use them with older tools. Here's how to fix that.
FIR Filter Implementation Comparisons
VHDL

FIR Filter Implementation Comparisons

Having created the pipelined adder tree component, time to compare it with other implementations to see what value it adds.