Technology Blogs

FPGA partial reconfiguration using a very basic demonstration design.

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…