We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "io"

Explaining Minimum Output Delays
FPGA

Explaining Minimum Output Delays

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
01 Signal Sampling
FPGA

01 Signal Sampling

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
Low Speed Serial I/O
FPGA

Low Speed Serial I/O

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…