We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "placement"

Explaining Minimum Output Delays
FPGA

Explaining Minimum Output Delays

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
Power Reduction using Vivado
FPGA

Power Reduction using Vivado

An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
Practical Control Set Reduction
FPGA

Practical Control Set Reduction

Checking that control set remapping delivers on the Xilinx promises.