library ieee;
  use ieee.std_logic_1164.all;
  use ieee.fixed_pkg.all;
library local;

entity quick_log2 is
  generic(
    data_width_g : positive := 16;
    frac_width_g : positive := 4;
    use_lut_g    : boolean  := true -- true more accurate, false better timing
  );
  port (
    clk    : in  std_logic;
    linear : in  std_logic_vector(data_width_g-1 downto 0);
    log    : out ufixed(local.math_pkg.ceil_log(data_width_g, 2)-1 downto -frac_width_g)
  );
end entity;


library ieee;
  use ieee.numeric_std_unsigned.all;

architecture rtl of quick_log2 is

  type lut_type is array (0 to 2**frac_width_g-1) of std_logic_vector(frac_width_g-1 downto 0);

  function log2_lut return lut_type is
    use ieee.math_real.log2;
    use ieee.math_real.round;
    variable ret : lut_type;
  begin
    for i in lut_type'range loop
      ret(i) := to_slv(
        integer(round(real(2**frac_width_g) * log2(real(1.0 + real(i)/real(2**frac_width_g))))),
        ret(i)'length
      );
    end loop;
    return ret;
  end function;

  constant log2_frac_lut_c : lut_type := log2_lut;

  function get_msb_pos(val : std_logic_vector) return integer is
  begin
    for i in val'range loop
      if val(i) = '1' then
        return i;
      end if;
    end loop;
    return 0;
  end function;

begin

  process(clk)

    variable msb_idx_v  : integer range 0 to data_width_g-1;
    variable mantissa_v : std_logic_vector(frac_width_g-1 downto 0);
    variable fraction_v : std_logic_vector(frac_width_g-1 downto 0);

  begin
    if rising_edge(clk) then
      -- Find MSB position (Integer part)
      msb_idx_v := get_msb_pos(linear);

      -- Extract fractional bits directly following the leading '1'
      -- Handles boundary cases where remaining bits are fewer than frac_width_g
      mantissa_v := (others => '0');
      for j in 0 to frac_width_g-1 loop
        if (msb_idx_v - 1 - j) >= 0 then
          mantissa_v(frac_width_g - 1 - j) := linear(msb_idx_v - 1 - j);
        else
          mantissa_v(frac_width_g - 1 - j) := '0';
        end if;
      end loop;

      -- Look up fractional bits
      if use_lut_g then
        -- Maximum error = 0.1074 for 4 fractional bits
        fraction_v := log2_frac_lut_c(to_integer(mantissa_v));
      else
        -- Really simple, note the log2_frac_lut_c is nearly output = input
        -- Maximum error = 0.1485 for 4 fractional bits
        fraction_v := mantissa_v;
      end if;

      -- Combined 8-bit result in unsigned fixed point Qm.f format where:
      --  * m = log2(data_width_g)-1
      --  * f = frac_width_g
      log <= to_ufixed(to_slv(msb_idx_v, 4) & fraction_v, log);
    end if;
  end process;

end architecture;

  -- Mathematically accurate log2 LUT for a 4-bit mantissa
  constant log2_frac_lut_c : lut_type := (
    X"0", X"1", X"3", X"4", X"5", X"6", X"7", X"8",
    X"9", X"A", X"B", X"C", X"D", X"E", X"F", X"F"
  );