FPGA partial reconfiguration using a very basic demonstration design.
VHDL
Assertion-based Verification in Intel's Free QuestaSim
Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
FPGA
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
FPGA
Determining A Device's Maximum Clock Speed
A proposed method for determining an FPGA device's maximum clock speed.
FPGA
Practical Control Set Reduction
Checking that control set remapping delivers on the Xilinx promises.
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
FPGA
Getting Started with FPGA and VHDL
I've been asked a few times how one gets started with FPGA design? Here are a few notes on the tools you can download for free and the existing websites that already cater for teaching VHDL.
FPGA
Verification of Clock Domain Crossing Topologies
There are too many ways in which it is possible to mess up clock domain crossings in digital electronics. This post explores Xilinx's report_cdc TCL command and how well it recognises some of the risks you may have missed.
FPGA
Verification of Clock Domain Crossing Timing Constraints and Exceptions
Applying timing exceptions for synchronising registers when crossing clock domains, and verifying the exceptions have been correctly applied and others have not been missed.
