My first proper attempt to use formal verification on an integer division operation.
C
FIR Filter Experiment with Vitis HLS
FIR filter experiment with Vitis HLS.
C
First Attempt at High Level Synthesis
My first attempt at using Vitis HLS to synthesise C code to logic.
VHDL
Cross-vendor Compatibility of VHDL Inferred RAM
The question came up at work, is inferred RAM compatible across different FPGA vendors?
FPGA
Dynamic Function eXchange
FPGA partial reconfiguration using a very basic demonstration design.
VHDL
Assertion-based Verification in Intel's Free QuestaSim
Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
FPGA
Script to compile Xilinx Primitives with Intel's FPGA Starter edition QuestaSim
Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.
FPGA
Determining A Device's Maximum Clock Speed
A proposed method for determining an FPGA device's maximum clock speed.
FPGA
Practical Control Set Reduction
Checking that control set remapping delivers on the Xilinx promises.
