FPGA partial reconfiguration using a very basic demonstration design.
FPGA
01 Signal Sampling
Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
VHDL
Assertion-based Verification in Intel's Free QuestaSim
Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
VHDL
Large Multiplexer Pipelined Efficiently by Recursion
Creating an excessively large multiplexer component that is arbitraily pipelined.
VHDL
Large Barrel Shift Pipelined by Iteration or Recursion
Creating an excessively large barrel shift component that is arbitraily pipelined.
VHDL
Multiple Bit Pseudorandom Binary Sequence
The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.
FPGA
Power Reduction using Vivado
An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
FPGA
Investigating Xilinx AXI IP and Registered Outputs
Investigating Xilinx AXI IP Cores, registered outputs and the AXI specification using equivalent components for the AXI stream split and join functions.
FPGA
Determining A Device's Maximum Clock Speed
A proposed method for determining an FPGA device's maximum clock speed.
