I found an excellent Log2() approximation solution from the Internet. This code allows the precision to be varied by number of fractional bits and then explores how the clock speed is affect.
C
FIR Filter Experiment with Vitis HLS
FIR filter experiment with Vitis HLS.
C
First Attempt at High Level Synthesis
My first attempt at using Vitis HLS to synthesise C code to logic.
VHDL
Cross-vendor Compatibility of VHDL Inferred RAM
The question came up at work, is inferred RAM compatible across different FPGA vendors?
FPGA
Low Speed Serial I/O Variable Delay Monitoring
Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.
FPGA
Dynamic Function eXchange with ICAP
With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
FPGA
Dynamic Function eXchange
FPGA partial reconfiguration using a very basic demonstration design.
FPGA
01 Signal Sampling
Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
VHDL
Assertion-based Verification in Intel's Free QuestaSim
Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
