Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "vhdl"

Low Speed Serial I/O Variable Delay Monitoring
FPGA

Low Speed Serial I/O Variable Delay Monitoring

Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.
Dynamic Function eXchange with ICAP
FPGA

Dynamic Function eXchange with ICAP

With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
Dynamic Function eXchange
FPGA

Dynamic Function eXchange

FPGA partial reconfiguration using a very basic demonstration design.
01 Signal Sampling
FPGA

01 Signal Sampling

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.
Assertion-based Verification in Intel's Free QuestaSim
VHDL

Assertion-based Verification in Intel's Free QuestaSim

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.
Large Multiplexer Pipelined Efficiently by Recursion
VHDL

Large Multiplexer Pipelined Efficiently by Recursion

Creating an excessively large multiplexer component that is arbitraily pipelined.
Large Barrel Shift Pipelined by Iteration or Recursion
VHDL

Large Barrel Shift Pipelined by Iteration or Recursion

Creating an excessively large barrel shift component that is arbitraily pipelined.
Multiple Bit Pseudorandom Binary Sequence
VHDL

Multiple Bit Pseudorandom Binary Sequence

The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.
Power Reduction using Vivado
FPGA

Power Reduction using Vivado

An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.