Technology Blogs

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.

FPGA partial reconfiguration using a very basic demonstration design.

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…

The ITU-T O.150 standard defines several methods of generating pseudorandom binary sequence meeting maximum sequences of zeros or ones.

Intel's FPGA Starter edition of QuestaSim no longer compiles the primitives for Xilinx's Vivado. Here's a batch file to achieve some of the same process.

Investigating Xilinx AXI IP Cores, registered outputs and the AXI specification using equivalent components for the AXI stream split and join functions.

A proposed method for determining an FPGA device's maximum clock speed.

Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.