We play with technology. Sometimes we discover things we think are worth sharing.

Tag: "tree"

Radix-n Fast Fourier Transforms (Part 3)
VHDL

Radix-n Fast Fourier Transforms (Part 3)

FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
FIR Filter Implementation Comparisons
VHDL

FIR Filter Implementation Comparisons

Having created the pipelined adder tree component, time to compare it with other implementations to see what value it adds.
Adder Trees Pipelined Efficiently by Recursion
VHDL

Adder Trees Pipelined Efficiently by Recursion

Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
Deriving AXI Crossbar Address Maps
FPGA

Deriving AXI Crossbar Address Maps

Some tips and tricks for correctly decoding an AXI crossbar address map.
Large Comparators Pipelined Efficiently by Recursion
VHDL

Large Comparators Pipelined Efficiently by Recursion

Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a mathematics problem, and once the VHDL construction has been completed, the EDA tools have a final twist.