We play with technology. Sometimes we discover things we think are worth sharing.
Tag: "routing"
FPGA
Explaining Minimum Output Delays
I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
FPGA
Dynamic Function eXchange
FPGA partial reconfiguration using a very basic demonstration design.
FPGA
Power Reduction using Vivado
An attempt to reduce power consumption of a simple design using Vivado's 'power_opt_design'.
FPGA
Practical Control Set Reduction
Checking that control set remapping delivers on the Xilinx promises.
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
