Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.
FIR Filter Experiment with Vitis HLS
C

FIR Filter Experiment with Vitis HLS

FIR filter experiment with Vitis HLS.
First Attempt at High Level Synthesis
C

First Attempt at High Level Synthesis

My first attempt at using Vitis HLS to synthesise C code to logic.
Cross-vendor Compatibility of VHDL Inferred RAM
VHDL

Cross-vendor Compatibility of VHDL Inferred RAM

The question came up at work, is inferred RAM compatible across different FPGA vendors?
Low Speed Serial I/O Variable Delay Monitoring
FPGA

Low Speed Serial I/O Variable Delay Monitoring

Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.
Dynamic Function eXchange with ICAP Driven by Software
FPGA

Dynamic Function eXchange with ICAP Driven by Software

With the previous success of reconfiguring removable partitions via the ICAP interface, what does the AXI-lite interface allow software to do?
Dynamic Function eXchange with ICAP
FPGA

Dynamic Function eXchange with ICAP

With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
Explaining Minimum Output Delays
FPGA

Explaining Minimum Output Delays

I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
Dynamic Function eXchange
FPGA

Dynamic Function eXchange

FPGA partial reconfiguration using a very basic demonstration design.
01 Signal Sampling
FPGA

01 Signal Sampling

Trialling an additional Low Speed I/O data ingest technique suggested by Eli Billauer.