I found an excellent Log2() approximation solution from the Internet. This code allows the precision to be varied by number of fractional bits and then explores how the clock speed is affect.
C
FIR Filter Experiment with Vitis HLS
FIR filter experiment with Vitis HLS.
C
First Attempt at High Level Synthesis
My first attempt at using Vitis HLS to synthesise C code to logic.
VHDL
Cross-vendor Compatibility of VHDL Inferred RAM
The question came up at work, is inferred RAM compatible across different FPGA vendors?
FPGA
Low Speed Serial I/O Variable Delay Monitoring
Using the Internal Logic Analyser in order to see how the IDELAY offset is selected on a real device.
FPGA
Dynamic Function eXchange with ICAP Driven by Software
With the previous success of reconfiguring removable partitions via the ICAP interface, what does the AXI-lite interface allow software to do?
FPGA
Dynamic Function eXchange with ICAP
With the previous success of creating the removable modules, how can they be programmed via the Internal Configuration Access Port?
FPGA
Explaining Minimum Output Delays
I feel frustrated by my lack of understanding about external timing constraints, and clearly this is shared by several others.
FPGA
Dynamic Function eXchange
FPGA partial reconfiguration using a very basic demonstration design.
