Technology Blogs

We play with technology. Sometimes we discover things we think are worth sharing.
Verification of Clock Domain Crossing Timing Constraints and Exceptions
FPGA

Verification of Clock Domain Crossing Timing Constraints and Exceptions

Applying timing exceptions for synchronising registers when crossing clock domains, and verifying the exceptions have been correctly applied and others have not been missed.
Using Certbot To Generate Certificates Without SSH Access
Bash

Using Certbot To Generate Certificates Without SSH Access

Let's Encrypt and Certbot provide ways to automate the maintenance of free HTTPS certificates for your website, but only if your hosting service has included the cPanel plugin or gives you SSH access. We present a solution that we've used for…
Radix-n Fast Fourier Transforms (Part 3)
VHDL

Radix-n Fast Fourier Transforms (Part 3)

FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
Radix-n Fast Fourier Transforms (Part 2)
VHDL

Radix-n Fast Fourier Transforms (Part 2)

FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
Radix-n Fast Fourier Transforms (Part 1)
VHDL

Radix-n Fast Fourier Transforms (Part 1)

FFTs are generally defined recursively, so how hard can it be to write a recursive VHDL implementation of an FFT that can scale to any number of inputs for any chosen radix?
Compiling VHDL For The Missing Fixed And Floating Point Libraries
VHDL

Compiling VHDL For The Missing Fixed And Floating Point Libraries

VHDL-2008 has added types sfixed, ufixed and float for fixed and floating point arithmetic, but you may struggle to use them with older tools. Here's how to fix that.
FIR Filter Implementation Comparisons
VHDL

FIR Filter Implementation Comparisons

Having created the pipelined adder tree component, time to compare it with other implementations to see what value it adds.
Adder Trees Pipelined Efficiently by Recursion
VHDL

Adder Trees Pipelined Efficiently by Recursion

Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
Notes on Fixing Hold Time Violations
FPGA

Notes on Fixing Hold Time Violations

Gathering advice on how to fix hold time violations with an emphasis on FPGA design.