Checking that control set remapping delivers on the Xilinx promises.
FPGA
Exploring Xilinx XPM Memory
The XPM_MEMORY components from Xilinx offer lots of facilities, even having more generics than ports. This means that the generics values need to be tailored carefully to be compatible. Is there a more convenient abstraction that can be derived for…
VHDL
A Crib For Formatting Strings in VHDL
VHDL solutions I keep searching the Internet for, so I've created a crib.
VHDL
AXI Stream Protocol Editing
Example use of the 'AXI Edit' component to convert a protocol.
VHDL
AXI Stream General Edit
A general way of editing an AXI stream using actions: pass, swap, drop, insert and pause.
VHDL
AXI Data Stream Width Conversion
Example code to convert 16-bit data to 8-bits in an AXI Data Stream.
Garmin-ConnectIQ
Monkey C In Application Logging
A simple method to replace Monkey C's System.println() for use in application executing on a watch.
FPGA
Taking Xilinx's Advice on Reducing Routing Congestion
I've been faced with the situation where the tools fail to create an image that meets timing, complaining about routing congestion. Here are some anecdotes about trying to follow Xilinx's advice.
TCL
Extracting Setup and Hold Times from Devices for Out of Context Synthesis
The present method of constraining the inputs and outputs of a design for out of context synthesis requires knowledge of the chosen devices timing characteristics. Previously these have been extracted from a timing report, and the build re-run. This…
