Having created the pipelined adder tree component, time to compare it with other implementations to see what value it adds.
VHDL
Adder Trees Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
VHDL
Comparison of ModelSim 'Signal Spies' and VHDL 'External Signals'
Example uses of ModelSim's Signal Spies and VHDL-2008's External Signals.
FPGA
Interpreting The AXI Protocol Specification for Testing
Interpreting the ARM AMBA AXI protocol specification so that hardware components can be successfully created and tested.
VHDL
Cascade Block RAMs for Larger Memories
Making the least of Xilinx BlockRAM "cascade logic" for performance.
VHDL
SRL Inferencing with Xilinx FPGAs
The inference of Xilinx SRLs is often believed to be dependent on the inclusion of a reset condition. Since the SRL does not have a reset input, it is logical that to infer use of SRLs, the HDL code must also exclude a reset pin. Or is it?
VHDL
Large Comparators Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a mathematics problem, and once the VHDL construction has been completed, the EDA tools have a final twist.
VHDL
Bus-width Polynomial Division Logic
Calculating the remainder after polynomial division modulo 2 multiple bits per clock cycle. This enables the calculation to keep pace with the presentation of a wide data bus. This article shows how VHDL and synthesis can automatically calculate the…
VHDL
Swapping Synchronous and LFSR Counters
Easily replace synchronous counters with equivalent LFSR-based fast counters.
