Log in
Register
Tech
Contact
Technology Blogs
We play with technology. Sometimes we discover things we think are worth sharing.
Copyright: All code in the posts are shared under the
MIT Open Source Licence
.
Front Page
Archives
Latest comments
Archives for: "September 2024"
FPGA
Determining A Device's Maximum Clock Speed
A proposed method for determining an FPGA device's maximum clock speed.
VHDL
Doulos Clock Domain Crossing Material
Doulos provide two CDC solutions that were new to me, or at least variations on others I had used. So I coded them up in VHDL to try them out.
