Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
FPGA
Visualising Clock Domain Crossings in Vivado
When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
FPGA
Specifying Boundary Timing Constraints in Vivado
How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.
FPGA
Interpreting The AXI Protocol Specification for Testing
Interpreting the ARM AMBA AXI protocol specification so that hardware components can be successfully created and tested.
VHDL
Cascade Block RAMs for Larger Memories
Making the least of Xilinx BlockRAM "cascade logic" for performance.
VHDL
SRL Inferencing with Xilinx FPGAs
The inference of Xilinx SRLs is often believed to be dependent on the inclusion of a reset condition. Since the SRL does not have a reset input, it is logical that to infer use of SRLs, the HDL code must also exclude a reset pin. Or is it?
VHDL
Large Comparators Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a mathematics problem, and once the VHDL construction has been completed, the EDA tools have a final twist.
VHDL
Bus-width Polynomial Division Logic
Calculating the remainder after polynomial division modulo 2 multiple bits per clock cycle. This enables the calculation to keep pace with the presentation of a wide data bus. This article shows how VHDL and synthesis can automatically calculate the…
VHDL
Swapping Synchronous and LFSR Counters
Easily replace synchronous counters with equivalent LFSR-based fast counters.
