Our design team has recently observed that Vivado has been struggling to get a licence later into long running compilations. These are some of the ideas I have developed to try and monitor the problem and make our compilations resilient to licence…
FPGA
Automating Code Review Design Checks in Vivado
Automating checks for transparent latches, asynchronous resets, no resets in Xilinx's Vivado synthesis tool.
FPGA
Visualising Clock Domain Crossings in Vivado
When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
FPGA
Specifying Boundary Timing Constraints in Vivado
How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.
