We play with technology. Sometimes we discover things we think are worth sharing.
Archives for: "August 2019"
VHDL
Large Comparators Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a mathematics problem, and once the VHDL construction has been completed, the EDA tools have a final twist.
VHDL
Bus-width Polynomial Division Logic
Calculating the remainder after polynomial division modulo 2 multiple bits per clock cycle. This enables the calculation to keep pace with the presentation of a wide data bus. This article shows how VHDL and synthesis can automatically calculate the…
VHDL
Swapping Synchronous and LFSR Counters
Easily replace synchronous counters with equivalent LFSR-based fast counters.
