We play with technology. Sometimes we discover things we think are worth sharing.
Archives for: "August 2021"
VHDL
Adder Trees Pipelined Efficiently by Recursion
Amusing myself with recursive structures in HDL that are entirely synthesisable and optimal in both size and clock speed. This is primarily a hierarchical construction problem made interesting by having to copy with a non-balance tree.
FPGA
Notes on Fixing Hold Time Violations
Gathering advice on how to fix hold time violations with an emphasis on FPGA design.