We play with technology. Sometimes we discover things we think are worth sharing.

Archives for: "December 2024"

Low Speed Serial I/O
FPGA

Low Speed Serial I/O

High speed serial I/O has been made simple to set up. It does however have a lower limit of clock speed, e.g. 300 MHz. Whilst the data rate can be lower than 300 Mb/s by using a chip select pin to negate the validity of some bits over time, that does…
Assertion-based Verification in Intel's Free QuestaSim
VHDL

Assertion-based Verification in Intel's Free QuestaSim

Getting started with Property Specification Language (PSL) using QuestaSim and VHDL-2008.