We play with technology. Sometimes we discover things we think are worth sharing.
Archives for: "September 2022"
FPGA
Managing Mean Time Between Failure in Xilinx Devices
The choice of synchroniser chain length is fundamental to any design including clock domain crossings, and directly affects the Mean Time Between Failure (MTBF). Xilinx does support determining the MTBF of your design but does little to assist in…
TCL
TCL/TK Graphical Display Driven By A VHDL Test Bench
An example TCK/TK graphical display driven by VHDL such that as signals change, the display reflects the new values.
