We play with technology. Sometimes we discover things we think are worth sharing.
Archives for: "May 2021"
FPGA
Visualising Clock Domain Crossings in Vivado
When picking up unfamiliar code with multiple clock domains, this visualisation technique can improve your understanding of which clocks drive each sequential primitive.
FPGA
Specifying Boundary Timing Constraints in Vivado
How to drive the XDC constraints file for input and output delays in Vivado. Some notes for something I keep needing to lookup.
Web Authoring
Reverse Engineering the Denon Amplifier Web API
We've just purchased a Denon AVR-X3700H AV amplifier. We're now reverse engineering how the web-based application works, and potentially the Android App too, so that we can detail what HTTP GET requests we can make when building our own automation…
FPGA
Interpreting The AXI Protocol Specification for Testing
Interpreting the ARM AMBA AXI protocol specification so that hardware components can be successfully created and tested.
